Scaling consideration of BiCMOS SRAMs

The authors present scaling considerations for BiCMOS static-RAMs (SRAMs) based on an experimental 4 K emitter-coupled-logic input/output (ECL I/O) BiCMOS SRAM design. The impact of scaling on the performance of the BiCMOS SRAM stems from the down-scaling of the integration size, which determines the parasitic capacitive load of the word lines and the bit lines. As a result, the access time of a scaled BiCMOS SRAM is determined mainly by the word-line and the bit-line delays. As for the ECL circuits, the scaled delay is mostly influenced by the reduction in the allocated power. According to the analysis, further integration of the BiCMOS SRAMs over 1 Mbits is limited by the evolution of the CMOS processing technology and the BiCMOS circuit design techniques, which can help resolve the access time disadvantage resulting from the increased size without a substantial power penalty