• DocumentCode
    2834299
  • Title

    Test minimization technique for multiple stuck-at faults of combinational circuit

  • Author

    Andreeva, V.

  • Author_Institution
    Tomsk State Univ., Tomsk, Russia
  • fYear
    2010
  • fDate
    17-20 Sept. 2010
  • Firstpage
    168
  • Lastpage
    170
  • Abstract
    In this paper the problem of test minimization technique for multiple stuck-at faults of combinational circuit derived from irredundant system sums-of-product (ISSOP) is considered. For minimizing of test length for considered circuit approach described in work [6] is used. The main steps of the minimization approach is a finding the root of the logical equation with a smaller rank and the extracting all the maximum compatible subsets.
  • Keywords
    combinational circuits; fault diagnosis; logic testing; combinational circuit; irredundant system sums-of-product; logical equation; maximum compatible subsets; stuck-at faults; test minimization; Boolean functions; Circuit faults; Combinational circuits; Equations; Logic gates; Minimization; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design & Test Symposium (EWDTS), 2010 East-West
  • Conference_Location
    St. Petersburg
  • Print_ISBN
    978-1-4244-9555-9
  • Type

    conf

  • DOI
    10.1109/EWDTS.2010.5742046
  • Filename
    5742046
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2834299