Packaging technologies for supercomputer system

The NEC SX-3 Model 44 supercomputer system has a maximum performance of 5.5 Gflops for the uniprocessor and 22 Gflops for the quad processor. The authors discuss packaging technology for the SX-3, which allows reduction of signal propagation delays between LSIs. It consists of 3 levels. The first level uses high-density connection technology that allows full exploitation of high-speed LSI chips. The authors developed an advanced chip carrier for this purpose referred to as the FTC (flipped TAB carrier). The second level is the multichip package level containing high-density FTCs prepared at the first level. The third level is a board level. The main focus is shortening of connecting wires between the MCPs (multichip packages). Other measures used were adoption of the FTC as an LSI chip carrier that allows implementation of an LSI with multiple terminals and high power, and adoption of a ceramic+polyimide structure as a multilayer substrate that yields high speed and high-density wiring