On the design of CMOS digital output drivers with controlled dI/dt

The authors consider the design of CMOS integrated digital output buffers for the driving of large capacitive loads. A strategy to obtain a triangular-like waveform of the output current is suggested and analyzed. A very fast output voltage switching is achieved while the voltage bumps induced on the supply line parasitic inductances are limited to a minimum. Equations for an optimum design are also given. As an example, the authors present a circuit architecture, where the peak value of the time derivative of the output current is proportional to a reference current