Optimal delay-power tradeoffs for replicative logic circuitry

Author

Eisele, Veronika ; Schmitt-Landsiedel, Doris

Author_Institution

Inst. of Electron. Design Autom., Tech. Univ. of Munich, Germany

fYear

1991

fDate

11-14 Jun 1991

Firstpage

2264

Abstract

A method for multiobjective optimization of replicative logic circuitry, like decoders, adders or comparators, is presented. The device dimensions are optimized with respect to signal delay, power dissipation, and area consumption. The fan out of the gates, the number of gates in every stage, and the operation mode of the circuit are taken into account. Posynomial gate-level macromodels are used to determine the circuit performance; therefore, efficient analytical multicriterion optimization techniques can be applied. With the new procedure, different architectural implementations of replicative combinatorial logic circuitry are systematically compared based on optimized device dimensions

Keywords

circuit layout CAD; integrated logic circuits; logic CAD; optimisation; adders; architectural implementations; area consumption; circuit performance; combinatorial logic; comparators; decoders; delay-power tradeoffs; fan out; gate-level macromodels; multicriterion optimization techniques; multiobjective optimization; number of gates; operation mode; optimized device dimensions; power dissipation; replicative logic circuitry; signal delay; Clocks; Combinatorial mathematics; Decoding; Delay; Frequency; Leakage current; Logic circuits; Logic design; Logic devices; Power dissipation;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991., IEEE International Sympoisum on

Print_ISBN

0-7803-0050-5

Type

conf

DOI

10.1109/ISCAS.1991.176831

Filename

176831