DocumentCode
2834470
Title
Exploring modeling and testing of NAND flash memories
Author
Di Carlo, Stefano ; Fabiano, Michele ; Piazza, Roberto ; Prinetto, Paolo
Author_Institution
Dipt. di Autom. ed Inf. (DAUIN), Politec. di Torino, Turin, Italy
fYear
2010
fDate
17-20 Sept. 2010
Firstpage
47
Lastpage
50
Abstract
Testing NAND flash memories is a very complex issue due to the rapid scaling down of the technology and the related floating gate reliability issues: as a consequence a complete and technology independent test is needed. Several faults and disturbances were identified both for NOR and NAND flash memories: however they has never been considered together as a whole. In this work we analyze all the possible fault models for NAND flash memories: thus we define a comprehensive and technology independent fault model for NAND Flash memories, for which a simple but comprehensive test method is presented.
Keywords
NAND circuits; flash memories; logic testing; NAND flash memories; NOR flash memories; comprehensive test method; fault model; Analytical models; Ash; Circuit faults; Flash memory; Logic gates; Reliability; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design & Test Symposium (EWDTS), 2010 East-West
Conference_Location
St. Petersburg
Print_ISBN
978-1-4244-9555-9
Type
conf
DOI
10.1109/EWDTS.2010.5742059
Filename
5742059
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