DocumentCode :
2834487
Title :
Analytical models for sizing of VLSI power/ground nets under electromigration, inductive and resistive constraints
Author :
Khanna, Sandeep ; Pitaksanonkul, Anucha ; Lursinsap, Chidchanok ; Techangam, Vites
Author_Institution :
Quality Semiconductor Inc., Santa Clara, CA, USA
fYear :
1991
fDate :
11-14 Jun 1991
Firstpage :
2272
Abstract :
The authors investigate the factors contributing to the sizing of the width of the power and ground (P/G) networks taking into account the constraints due to electromigration, inductance, and resistance. It is assumed that the lengths for all paths and corresponding currents have already been computed. Analytical models are proposed for these constraints. The models can be applied directly to the power/ground structure. After power and ground routing, the length of each power path is known. The initial width of each path depends on the power/ground structure. The analytical models are applied at the last step to resize the lines
Keywords :
VLSI; circuit layout CAD; electric resistance; electromigration; inductance; modelling; VLSI; analytical models; electromigration constraints; ground net sizing; inductance constraints; path width sizing; power net sizing; resistance constraints; resistive constraints; Analytical models; Conductors; Current density; Electromigration; Inductance; MOSFETs; Metallization; Strips; Very large scale integration; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN :
0-7803-0050-5
Type :
conf
DOI :
10.1109/ISCAS.1991.176833
Filename :
176833
Link To Document :
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