DocumentCode
2834499
Title
A waveform relaxation method applicable to bipolar digital circuits
Author
Nakano, Mikio ; Mae, Youichhu ; Shirakawa, Isao
Author_Institution
Toshiba Corp., Kawasaki, Japan
fYear
1991
fDate
11-14 Jun 1991
Firstpage
2276
Abstract
The authors describe a method of implementing waveform relaxation for bipolar digital circuits. The key is to partition not only a given bipolar circuit into subcircuits but also the whole simulation time-interval into subintervals (windows), dynamically according to changes in operation status of specified bipolar transistors, so that in a given window every subcircuit can be simulated in parallel by means of the waveform relaxation. A number of implementation results are also shown to reveal how this waveform relaxation approach is useful in practice for bipolar digital circuits
Keywords
bipolar integrated circuits; circuit analysis computing; digital integrated circuits; relaxation theory; waveform analysis; bipolar digital circuits; circuit partitioning; parallel simulation; time partitioning; waveform relaxation method; windowing; Bipolar transistor circuits; Bipolar transistors; Circuit simulation; Digital circuits; Information systems; MOSFETs; Modeling; Relaxation methods; Systems engineering and theory; Transient analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN
0-7803-0050-5
Type
conf
DOI
10.1109/ISCAS.1991.176834
Filename
176834
Link To Document