A solution to high performance acceleration of digital system design

Describes a hardware simulation accelerator that has been designed to handle components of extreme complexity (such as microprocessors) as well as incorporating advanced architectures to provide maximum simulation speed for low level primitives (e.g. ASICS). The issue of mixed-level component modelling for system design is considered first, and then the architecture of the accelerator, known as the GigaLOGICIAN is examined in conjunction with the design objectives