ESL design methodology for architecture exploration

With the increasing complexity of digital systems, digital design techniques have evolved and got to a higher abstraction level which is Electronic System Level (ESL). Designing in this abstraction level needs new languages and methods to describe, synthesize, test, and verify systems. ESL design methodology is a way to handle the complexity of designing digital systems, and decrease time-to-market by starting the design from higher abstraction level than Register Transfer Level (RTL). Transaction Level Modeling (TLM) has emerged in the direction of system level design. TLM is originally based on high level programming languages such as C++ and SystemC. In this paper a hardware-aware ESL design methodology is proposed. The proposed methodology includes several levels containing various architecture models and guidelines for design at each level. A Test Data Compression (TDC) system is implemented as a case study using TLM-2.0 standard.