Between standard cells and transistors: Layout templates for Regular Fabrics

Design rules for small process node become more restrictive and more complex nowadays. The usage of strongly predefined structures for layout design is the way to cope with the complexity of circuit design within the limits of design rules. This paper introduces an approach to design logic blocks within the limits of regular layout using pre-generated layout templates. Proposed technique skips the hierarchy of standard cells and uses templates as minimal functional elements. We introduce logic instrument to describe the functionality of templates and demonstrate examples of template-based synthesis solutions. We show that the template-based approach can significantly reduce design area in comparison with standard cells approach.