Hierarchical test strategy planning based on cost evaluation

The need for design for testability (DFT) is now widely accepted as an important part of integrated circuit design. The proposed test planner seeks to aid the designer in choosing the optimum DFT strategy for a particular design, keeping in mind market trends and company resources. A knowledge base is used to hold test method data, which are compared using a hierarchical, parametrised cost model. An inference engine will use the results of a testability analysis of the design blocks together with the knowledge base and the cost model predictions to make heuristic DFT choices, which will then be evaluated. The test planner will be linked with design tools for easy transfer of design information