DocumentCode :
2834773
Title :
Unfolding and retiming for high-level DSP synthesis
Author :
Lucke, Lori E. ; Brown, Andrew P. ; Parhi, Keshab K.
Author_Institution :
Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
fYear :
1991
fDate :
11-14 Jun 1991
Firstpage :
2351
Abstract :
A method of determining the minimum unfolding factor needed to synthesize a data path for a given sample rate is presented. Minimizing the unfolding factor is important because the time complexity for scheduling and allocation increases linearly with the unfolding factor. The authors discuss the iterative algorithm which calculates the minimum unfolding factor necessary to achieve a given sample rate with and without retiming. This algorithm is utilized within the MARS (the Minnesota architecture synthesis) design system to preprocess a dataflow graph prior to resource scheduling and allocation
Keywords :
computer architecture; digital signal processing chips; graph theory; resource allocation; scheduling; DSP synthesis; MARS; Minnesota architecture synthesis; dataflow graph; design system; iterative algorithm; minimum unfolding factor; resource scheduling; retiming; sample rate; time complexity; Computer architecture; Concurrent computing; Digital signal processing; Iterative algorithms; Mars; Processor scheduling; Resource management; Scheduling algorithm; Signal processing algorithms; Signal synthesis;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN :
0-7803-0050-5
Type :
conf
DOI :
10.1109/ISCAS.1991.176850
Filename :
176850
Link To Document :
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