Residue Arithmetic in FPGA Matrices

Author

Tomczak, Tadeusz

Author_Institution

Tadeusz Tomczak

fYear

2006

fDate

25-27 May 2006

Firstpage

297

Lastpage

305

Abstract

In this work, presented is the methodology of designing residue generators and arithmetic units for modern FPGA matrices. The proposed algorithms take advantage of dedicated logic for high-speed arithmetic present in Xilinx Spartan-2 and Virtex FPGA families. Comparing to implementations published so far, which are based mainly on look_up table solutions, new method results in better area-time efficiency, especially for medium and large moduli. The proposed units can be used in cryptography, fault tolerant computing and DSP algorithms

Keywords

field programmable gate arrays; logic design; residue number systems; DSP algorithm; FPGA matrices; Virtex FPGA families; Xilinx Spartan-2; arithmetic units; cryptography; dedicated logic; fault tolerant computing; look_up table solutions; residue arithmetic; residue generators design; Adders; Arithmetic; Calculus; Circuits; Cryptography; Design methodology; Digital signal processing; Fault tolerant systems; Field programmable gate arrays; Read only memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Dependability of Computer Systems, 2006. DepCos-RELCOMEX '06. International Conference on

Conference_Location

Szklarska Poreba

Print_ISBN

0-7695-2565-2

Type

conf

DOI

10.1109/DEPCOS-RELCOMEX.2006.43

Filename

4024062

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2834975