Fast timing analysis of VLSI circuits: a dynamic and hierarchical approach

A new and efficient procedure is proposed to evaluate the timing performance of VLSI circuits with circuit-level accuracy. The efficiency is obtained by dynamically changing the circuit hierarchy level and the delay model during the analysis. The analysis is performed at high level to rapidly identify the critical portions of the circuit. These critical portions are then successively studied at a more detailed level for maximal accuracy. This new procedure, which was implemented and applied to several large circuits, is shown to significantly reduce the analysis time