Title :
An accurate timing model for gate-level simulation of MOS circuits
Author :
Gai, S. ; Lioy, P. ; Montessoro, L.
Author_Institution :
Politecnico di Torino, Italy
Abstract :
The authors describe an accurate delay model for gate-level simulation of digital MOS circuits. Results from electrical-level simulation are given to present evidence that input-dependent, state-dependent delays as well as charge-storage effects must be considered in addition to intrinsic and load-dependent delays. A comprehensive simulation algorithm with limited overhead is discussed. It takes into account all these factors and it is fully compatible with event-driven selective-trace simulation
Keywords :
MOS integrated circuits; circuit analysis computing; delays; digital integrated circuits; digital simulation; charge-storage effects; delay model; digital MOS circuits; electrical-level simulation; gate-level simulation; load-dependent delays; simulation algorithm; state-dependent delays; timing model; Accuracy; Circuit faults; Circuit simulation; Computational modeling; Delay effects; Discrete event simulation; Impedance; Logic circuits; Logic design; Timing;
Conference_Titel :
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN :
0-7803-0050-5
DOI :
10.1109/ISCAS.1991.176863
