Generalized faulty block model for automatic test pattern generation

This paper presents work aimed at developing automatic test pattern generation algorithms and methods based on continuous approach to digital circuits modeling. We explore the idea of solving test search problem by means of continuous optimization. Here we introduce a generalized faulty block model providing a common approach to different fault types modeling at the test pattern generation phase. Presented algorithms and methods are implemented in an ATPG system. We report the experimental results of test pattern generation for stuck-at faults in combinational circuits (ISCAC´85 benchmarks), and also for bridging faults in sequential circuits (ISCAS´89 benchmarks).