FREP: A soft error resilient pipelined RISC architecture

Author

Kumar, Viney ; Choudhary, Rahul Raj ; Singh, Virendra

Author_Institution

Centre for Electron. Design & Technol., Indian Inst. of Sci., Bangalore, India

fYear

2010

fDate

17-20 Sept. 2010

Firstpage

330

Lastpage

333

Abstract

Soft error has become one of the major areas of attention with the device scaling and large scale integration. Lot of variants for superscalar architecture were proposed with focus on program re-execution, thread re-execution and instruction re-execution. In this paper we proposed a fault tolerant micro-architecture of pipelined RISC. The proposed architecture, Floating Resources Extended pipeline (FREP), re-executes the instructions using extended pipeline stages. The instructions are re-executed by hybrid architecture with a suitable combination of space and time redundancy.

Keywords

fault tolerance; large scale integration; pipeline processing; reduced instruction set computing; FREP; fault tolerant microarchitecture; floating resource extended pipeline; hybrid architecture; instruction re-execution; program re-execution; soft error resilient pipelined RISC architecture; superscalar architecture; thread re-execution; Computer architecture; Fault tolerant systems; Hardware; Pipelines; Reduced instruction set computing; Redundancy; Fault-tolerance; Instruction Reexecution; Pipelined RISC; Soft error mitigation;

fLanguage

English

Publisher

ieee

Conference_Titel

Design & Test Symposium (EWDTS), 2010 East-West

Conference_Location

St. Petersburg

Print_ISBN

978-1-4244-9555-9

Type

conf

DOI

10.1109/EWDTS.2010.5742103

Filename

5742103