• DocumentCode
    2835427
  • Title

    Testing and verification of HDL-models for SoC components

  • Author

    Hahanov, Vladimir ; Hahanova, Irina ; Umerah, Ngene Christopher ; Yves, Tiecoura

  • Author_Institution
    Comput. Eng. Fac., Kharkov Nat. Univ. of Radioelectron., Kharkov, Ukraine
  • fYear
    2010
  • fDate
    17-20 Sept. 2010
  • Firstpage
    77
  • Lastpage
    82
  • Abstract
    The testing and verification technology for system HDL models, focused to the significant improvement of the quality of design components for digital systems on chips and reduction the development time (time-to-market) by using the simulation environment, testable analysis of the logical structure HDL-program and the optimal placement of assertion engine is proposed.
  • Keywords
    hardware description languages; system-on-chip; SoC components; assertion engine; digital systems; logical structure HDL-program; testable analysis; testing technology; time-to-market; verification technology; Analytical models; Controllability; Engines; Observability; Registers; Software; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design & Test Symposium (EWDTS), 2010 East-West
  • Conference_Location
    St. Petersburg
  • Print_ISBN
    978-1-4244-9555-9
  • Type

    conf

  • DOI
    10.1109/EWDTS.2010.5742112
  • Filename
    5742112
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2835427