Performance enhancements in the superscalar i960MM embedded microprocessor

Author

McGeady, S. ; Steck, R. ; Hinton, G. ; Bajwa, A.

Author_Institution

Intel. Corp., Hillsboro, OR, USA

fYear

1991

fDate

Feb. 25 1991-March 1 1991

Firstpage

4

Lastpage

7

Abstract

Continued research into Intel´s i960 architecture has resulted in the development of performance improvements beyond those implemented in the i960CA microprocessor. These improvements allow additional superscalar dispatch opportunities, reduce memory access delays, and enhance the performance of specific instructions. The i960MM microprocessor is an implementation of these performance enhancements. Together, these enhancements can increase the performance of certain applications by 25% to 100%. Additionally, the i960MM includes an implementation of a full-function floating-point unit. Performance of 27 MFLOPs (single precision) and 16 MFLOPS (double precision) was achieved on the Linpack benchmarks at 40 MHz.<>

Keywords

microprocessor chips; performance evaluation; 16 MFLOPS; 27 MFLOPS; 40 MHz; Intel i960MM superscalar microprocessor; Linpack benchmarks; full-function floating-point unit; performance; Algorithms; Arithmetic; Clocks; Decoding; Delay; Dispatching; Memory architecture; Memory management; Microprocessors; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Compcon Spring '91. Digest of Papers

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-8186-2134-6

Type

conf

DOI

10.1109/CMPCON.1991.128774

Filename

128774