Implementation of RISC Processor on FPGA

A true 16-bit RISC processor has been designed using VHDL. Hierarchical approach has been used so that basic units can be modeled using behavioral programming. These basic units are combined using structural programming. Four stage (viz. instruction fetch stage, instruction decode stage, execution stage and memory/IO-writeback stage) pipelining is used to improve the overall CPI (clock cycles per instruction). Hardwired control approach is used to design the control unit as against microprogrammed control approach in conventional CISC processor. The processor has one input port, one output port and six hardware vectored interrupts along with 16-bit address bus and 16-bit data bus. Structural hazards are dealt with the implementation of prefetch unit, data hazards are dealt with forwarding and control hazards are dealt with flushing and stalling. The design has been implemented on FPGA for verification purpose.