Bipolar ECL implementation of SPARC

Author

Agrawal, Anant ; Brown, Emil W. ; Murata, Dave ; Petolino, Joseph

Author_Institution

Sun Microsyst. Inc., Mountain View, CA, USA

fYear

1989

fDate

22-24 Nov 1989

Firstpage

82

Lastpage

86

Abstract

The scalable processor architecture (SPARC) defines a general purpose 32 bit RISC processor architecture. The simple nature of the architecture provides a migration path to higher performance levels as new technologies become available. The goal was to design an architecture that would scale with, or track, improvements in the circuit technology. It has been implemented in gate arrays, full custom CMOS and bipolar emitter coupled logic (ECL) technologies by four different vendors. A number of implementations in other technologies including BiCMOS and GaAs are underway. A description is given of the B5000, the bipolar ECL implementation of the SPARC architecture. Also covered are some of the system level considerations that influenced the design of the processor

Keywords

bipolar integrated circuits; emitter-coupled logic; microprocessor chips; reduced instruction set computing; 32 bit; B5000; RISC processor architecture; SPARC; emitter coupled logic; scalable processor architecture; BiCMOS integrated circuits; CMOS technology; Gallium arsenide; Integrated circuit noise; Power transmission lines; Process design; Propagation delay; Silicon; Sun; Working environment noise;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON '89. Fourth IEEE Region 10 International Conference

Conference_Location

Bombay

Type

conf

DOI

10.1109/TENCON.1989.176900

Filename

176900