A superpipeline approach to the MIPS architecture

The next-generation MIPS CMOS microprocessor, the R4000, uses a technique called superpipelining to achieve a high level of performance. The authors discuss the evolution of the R4000 pipeline from the R3000 pipeline and the reasons why a superpipelined microarchitecture is chosen. First, there are no instruction issue restrictions with the R4000 superpipeline, as there would have been in a superscalar implementation. Various combinations of independent instructions, including ALU (arithmetic logic unit)/ALU and load/load can be executed without any pipeline stalls. The compiler is also simpler and instruction scheduling can be more efficient. Finally, there is no need to replicate functional units, as would be necessary in a superscalar implementation.<>