Experiments with ABIST test methodology applied to path delay fault testing

Author

Manikandan, P. ; Larsen, Bjørn B. ; Aas, Einar J.

Author_Institution

Electron. & Telecommun. Eng., Norwegian Univ. of Sci. & Technol., Trondheim, Norway

fYear

2010

fDate

17-20 Sept. 2010

Firstpage

59

Lastpage

63

Abstract

This paper presents SIC based test stimuli with Arithmetic Built in Self-Test (ABIST) concept in order to detect the path delay faults. The presented generator with ABIST stimuli is quite useful for detecting the K-longest path-delay faults of the microprocessor. This paper extends the work of Ø. Gjermundnes and presents its application and validation to the Intel 8051 microprocessor. The experimental results of this work with the given test case microprocessor allows us to validate the proposed test method is effective by the obtained fault coverage.

Keywords

built-in self test; delays; fault diagnosis; integrated circuit testing; microprocessor chips; ABIST test methodology; Intel 8051 microprocessor; K-longest path-delay fault detection; SIC based test stimuli; arithmetic built in self-test; path delay fault testing; single input change; Built-in self-test; Circuit faults; Delay; Logic gates; Microprocessors; Silicon carbide; Arithmetic; Built-In Self Test; Path Delay Fault Testing; Test Patterns;

fLanguage

English

Publisher

ieee

Conference_Titel

Design & Test Symposium (EWDTS), 2010 East-West

Conference_Location

St. Petersburg

Print_ISBN

978-1-4244-9555-9

Type

conf

DOI

10.1109/EWDTS.2010.5742129

Filename

5742129