A multichannel TDC based on ring-delay time multiplexer: A prototype

We have designed and implemented on a Xilinx Spartan HE FPGA a highly integrated time-multiplexing device by means of using a ring-delay loop. This idea grow out of Time Multiplexer introduced in NSS-2005 conference at Puertorico[l]. Single ring-delay is designed as a simple fixed loop delay by feedback. A 4+4 bit input value allows fixing the delay time amount as number of loop delay cycle: first 4 bit holds delay time of all input signal and second marks the output delay-slot. Different input signals are putted into as many delay-ring everyone with different value of 4 bit delay slot number. So, several channels can be merged into one channel delayed with different time, 150ns incremented. As a consequence, usage of one multi-hit channel to measure timing of up to 16 channels is possible if low rate of input signal is foreseen. Timing measurements show a max RMS jitter, for 16 ring-delay cycle, lower than 1 ns for about 2,4 mus of time delay, likely a passable contribution to timing misalignments.