• DocumentCode
    2836022
  • Title

    Parallel processing architecture for high performance digital signal processing

  • Author

    Crosetto, D. ; Dobinson, R.W. ; Martin, Benoit

  • Author_Institution
    CERN, Geneva, Switzerland
  • fYear
    1989
  • fDate
    22-24 Nov 1989
  • Firstpage
    201
  • Lastpage
    204
  • Abstract
    Currently, available digital signal processors (DSPs) offer extremely high computational performance, yet no convenient mechanism is available to solve the interconnection problem. Transputers are designed as building blocks for large processor arrays. Both hardware and software support the distribution of processes across configurations of multiple processors in a scalable way. An array of processors can be reconfigured by means of commercially available crossbar switches. A module is described that integrates the computing power of the DSP with the communication facilities of the transputer in an industry standard package
  • Keywords
    digital signal processing chips; multiprocessor interconnection networks; parallel architectures; transputers; crossbar switches; high performance digital signal processing; interconnection; transputer; Communication industry; Communication switching; Computer architecture; Computer industry; Digital signal processing; Digital signal processors; Hardware; High performance computing; Parallel processing; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    TENCON '89. Fourth IEEE Region 10 International Conference
  • Conference_Location
    Bombay
  • Type

    conf

  • DOI
    10.1109/TENCON.1989.176924
  • Filename
    176924