DocumentCode
2836056
Title
Testable combinational circuit design based on ZDD-implementation of ISOP Boolean function
Author
Ostanin, S. ; Muchamedov, R.
Author_Institution
Tomsk State Univ., Tomsk, Russia
fYear
2010
fDate
17-20 Sept. 2010
Firstpage
171
Lastpage
174
Abstract
It is found out that a set of test patterns for all multiple stuck-at faults at the CLBs poles of combinational circuit in the frame of FPGA technology coincides with the set of test for all single stuck-at faults of irredundant sum-of-products describing the combinational circuit behavior. The combinational circuit designed based on ZDD-implementation of irredundant sum-of-products.
Keywords
Boolean functions; combinational circuits; fault diagnosis; field programmable gate arrays; logic testing; FPGA technology; ISOP boolean function; ZDD-implementation; irredundant sum-of-products; multiple stuck-at faults; testable combinational circuit design; Boolean functions; Circuit faults; Combinational circuits; Data structures; Design automation; Field programmable gate arrays; Logic gates;
fLanguage
English
Publisher
ieee
Conference_Titel
Design & Test Symposium (EWDTS), 2010 East-West
Conference_Location
St. Petersburg
Print_ISBN
978-1-4244-9555-9
Type
conf
DOI
10.1109/EWDTS.2010.5742153
Filename
5742153
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