Virtual tester development using HDL/PLI

As digital systems become more complex, testing these complicated systems faces more challenges. One extreme is to use an ATE that tests our chip under control of a complex high level test program. Unfortunately the ATE is incapable of performing at-speed testing on a chip. The other extreme is to embed a complicated BIST hardware inside the chip that is responsible of testing the whole chip. This is a great idea but unfortunately occupies the valuable available area on the die that must be used for implementing ever increasing demand for digital functionality. In addition, BIST insertion leads to power and timing overhead and a drop in yield. In this paper we propose an intermediate method we call virtual tester, an interfacing hardware sits between ATE and a chip. ATE triggers the virtual tester and after that all testing procedure is performed under the control of the virtual tester at the native speed of the under test chip.