DocumentCode
2836604
Title
High-speed, area-efficient FPGA-based floating-point multiplier
Author
Aty, Gh A. ; Hussein, Aziza I. ; Ashour, I.S. ; Mones, M.
Author_Institution
Electron. Dept., Nat. Telecommun. Inst., Cairo, Egypt
fYear
2003
fDate
11-11 Dec. 2003
Firstpage
274
Lastpage
277
Abstract
In this paper, a floating-point multiplier with high speed and area efficient is presented. The multiplier is designed, optimized, and implemented on an FPGA based system. A comparison between the results of the proposed design and a previously reported one is provided. The effect of rounding on the area, speed, and accuracy for three different configurations is examined.
Keywords
analogue multipliers; field programmable gate arrays; floating point arithmetic; high-speed area-efficient FPGA-based floating-point multiplier; optimisation; Design optimization; Educational institutions; Field programmable gate arrays; Floating-point arithmetic; Hardware design languages; High level languages; IEEE members; Signal processing; Systems engineering and theory; Telecommunication computing;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics, 2003. ICM 2003. Proceedings of the 15th International Conference on
Conference_Location
Cairo, Egypt
Print_ISBN
977-05-2010-1
Type
conf
DOI
10.1109/ICM.2003.237828
Filename
1287799
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