The design and development of a fail safe interlocking system using microprocessors for Indian Railways

A fail safe route interlocking system based on microprocessors has been developed for Indian Railways. The design is based on an new approach that attempts to reduce the system complexity and attain a high safety standard by: (a) assigning appropriate levels of safety to the different functions of the system depending upon their criticality and implementing them through proper design techniques, and (b) modeling the system into a process of token flow between a number of hierarchical layers. A software package named SPRINT (simulation program for route interlocking) has been developed and can be used to simulate a given station yard by feeding the yard data in a predetermined format. The program can simulate the interlocking system along with its control environment and can be used for design validation and testing of new designs for route railway interlocking systems. The system design is based on a system architecture called FIRM (fail safe interlocking system for railways using microprocessors). The system architecture is described and field trial results are also presented