A high performance systolic IIR filter architecture

A novel bit-level systolic array architecture for implementing bit parallel IIR filter sections is presented. The fundamental obstacle of pipeline latency in recursive structures is overcome by the use of an alternative form of arithmetic which allows computations to proceed most significant digit first. In combination with bit-level feedback this allows the fine-grain pipelining of recursive structures operating on bit-parallel data. The achieved throughput is comparable with conventional flow-through (non-recursive) systolic architectures