A bit level CMOS/SOS convolver

Over the past few years the design of integrated circuits for digital signal processing has been aided by architectural developments such as the bit level systolic array. In particular several bit level systolic architectures for finite sequence convolution and correlation, and for inner product computation have been proposed. The architectures have progressively improved cell utilisation and data routing leading to increased data throughput and decreased circuit complexity. The device presented (commonly termed a `convolver´) is based upon some of the more recent advances in bit level systolic array architectures. The practical implementation of the device which computes finite sequence convolution is discussed