• DocumentCode
    283825
  • Title

    Test generation for combinational circuits with multiple faults

  • Author

    Takahashi, Hiroshi ; Iuchi, Nobukage ; Takamatsu, Yuzo

  • Author_Institution
    Dept. of Comput. Sci., Fac. of Eng., Ehime Univ., Matsuyama, Japan
  • fYear
    1991
  • fDate
    26-27 Sep 1991
  • Firstpage
    212
  • Lastpage
    217
  • Abstract
    A test generated under the single-fault assumption may be invalid for the combinational circuit with multiple faults because of masking among them. The authors propose a new test generation algorithm for combinational circuits with multiple faults. A property of a valid test which can detect a target fault regardless of the presence of any other fault is studied and it is shown that a pair of input vectors is necessary for the valid test of a target fault. Next, an algorithm for generating a single sensitized path using a seven-valued calculus and a decision algorithm for finding a completely single sensitized path are presented. Finally, experimental results on several benchmark circuits are given
  • Keywords
    automatic testing; combinatorial circuits; logic testing; combinational circuits; decision algorithm; multiple faults; sensitized path; seven-valued calculus; test generation algorithm; Benchmark testing; Calculus; Circuit faults; Circuit testing; Combinational circuits; Computer science; Electrical fault detection; Fault detection;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Fault Tolerant Systems, 1991. Proceedings., Pacific Rim International Symposium on
  • Conference_Location
    Kawasaki
  • Print_ISBN
    0-8186-2275-X
  • Type

    conf

  • DOI
    10.1109/{RFTS.1991.212943
  • Filename
    212943