A harmonic signal generator based on DDS and SOPC

A harmonic signal generator with adjustable frequency, phase and harmonic proportion is designed in this paper. The design of this harmonic signal generator is based on direct digital frequency synthesis (DDS) technology and the idea of System on a Programmable Chip (SOPC). The classic structure of DDS is introduced and a kind of compression ROM is designed. Then, the DDS core with compression ROM is compiled using Quartus II by VHDL language. As a kind of processor which is supplied by Atera Inc., the soft core, Nois II is embedded on FPGA chip. Using Nois II and other modules, a system is designed on one single FPGA chip. The performances such as integration, expansibility are very much improved. The principle of DDS is discussed particularly; the optimized structure of DDS core and the design SOPC on single FPGA are presented in this paper.