Comparison of aliasing probability for multiple MISRs and M-stage MISRs with m inputs

Author

Iwasaki, Kazuhiko ; Feng, Shou-Ping ; Fujiwara, Tom ; Kasami, Tadao

Author_Institution

Dept. of Inf. & Comput. Sci., Fac. of Eng., Chiba Univ., Japan

fYear

1991

fDate

26-27 Sep 1991

Firstpage

90

Lastpage

95

Abstract

MISRs are widely used as signature circuits for VLSI built-in self-tests. To improve the aliasing probability of MISRs, multiple MISRs and M-stage MISRs with m inputs are available, where M is greater than m. The aliasing probability as a function of the test length for these signature circuits is analyzed for a binary symmetric channel. It is shown that the peak aliasing probability of the double MISRs is less than that of an M-stage MISR with m inputs. It is also shown that the final aliasing probability for a multiple MISR with d MISRs is 2^-dm and that for an M-stage MISR with m inputs is 2^-M if it is characterized by a primitive polynomial. The double MISR is recommended to reduce the aliasing probability of signature circuits

Keywords

VLSI; built-in self test; integrated circuit testing; logic testing; probability; M-stage MISRs; VLSI built-in self-tests; aliasing probability; binary symmetric channel; double MISR; multiple MISRs; primitive polynomial; signature circuits; test length; Circuit testing; Equations; Linear code; Parity check codes; Polynomials; Probability; Reed-Solomon codes; Registers; Sequential circuits; Vectors;

fLanguage

English

Publisher

ieee

Conference_Titel

Fault Tolerant Systems, 1991. Proceedings., Pacific Rim International Symposium on

Conference_Location

Kawasaki

Print_ISBN

0-8186-2275-X

Type

conf

DOI

10.1109/{RFTS.1991.212962

Filename

212962