Design of Synchronous and Asynchronous Architectures for DFT based Adaptive Equalizer

This paper presents the design of synchronous and asynchronous architectures for a Discrete Fourier Transform (DFT) based Finite Impulse Response (FIR) filter. The one dimensional filter is based on the delayed Least Mean Squares (DLMS) algorithm. The architecture is derived for a 1×4 array of processing elements. The proposed synchronous architecture is applied in adaptive equalization and the convergence results are analyzed using Matlab. The functionality of the architecture is verified by simulation via Actel¿s Veribest VHDL simulator. The synchronous architecture is modified to operate in asynchronous mode by implementing a two phase handshaking protocol between the processing elements (PEs). The performance of the proposed architectures is analyzed in terms of speed up, adaptation delay and throughput. The proposed DFT based DLMS systolic architecture leads to faster convergence when compared to conventional DLMS systolic architecture. In the asynchronous architecture the processors are clock independent. This reduces the adaptation delay and increases the throughput. The architectures are highly modular and very much suitable for VLSI implementation.