DocumentCode :
2838928
Title :
Implementation of FPGA based DSP module for CW Doppler radar: Preliminary results
Author :
Terauds, M.
Author_Institution :
Fac. of Electron. & Telecommun., Riga Tech. Univ., Riga, Latvia
fYear :
2012
fDate :
12-13 Nov. 2012
Firstpage :
1
Lastpage :
6
Abstract :
This paper presents development and implementation of the Field-Programmable Gate Arrays (FPGA) of a novel Digital Signal Processing (DSP) module for the 24 GHz continuous wave (CW) Doppler radar. The module utilizes the well-known zero-crossing algorithm, relative simple signal filtering, iterative search method and the scattering centers model. The module is constructed to detect vehicles; it estimates its velocity, lane, and shape. Preliminary results of the lane and vehicle length estimation in case of two lanes are provided. VHDL code has been generated and necessary FGPA device resources for basic stages of DSP are estimated. Implementable VDHL code generation of novel algorithm is based on Simulink HDL coder.
Keywords :
Doppler radar; codecs; codes; digital signal processing chips; field programmable gate arrays; hardware description languages; radar signal processing; CW Doppler radar; CW doppler radar; DSP module; FGPA device; FPGA implementation; Simulink HDL coder; VDHL code generation; VHDL code; continuous wave Doppler radar; digital signal processing; field-programmable gate arrays; iterative search method; preliminary results; scattering centers model; signal filtering; zero-crossing algorithm; Digital signal processing; Doppler radar; Doppler shift; Scattering; Signal processing algorithms; Vehicles; CW radar; Doppler radar; FPGA implementation; road traffic control; scattering centres model; vehicle classification; zero-crossing algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
NORCHIP, 2012
Conference_Location :
Cpenhagen
Print_ISBN :
978-1-4673-2221-8
Electronic_ISBN :
978-1-4673-2222-5
Type :
conf
DOI :
10.1109/NORCHP.2012.6403117
Filename :
6403117
Link To Document :
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