A 90nm CMOS gated-ring-oscillator-based 2-dimension Vernier time-to-digital converter

Author

Ping Lu ; Andreani, Pietro ; Liscidini, Antonio

Author_Institution

Dept. of Electr. & Inf. Technol., Lund Univ., Lund, Sweden

fYear

2012

fDate

12-13 Nov. 2012

Firstpage

1

Lastpage

4

Abstract

Two branches of gated ring oscillators (GRO) act as the delay lines in 2-dimension Vernier time-to-digital converter (TDC). The proposed architecture reduces dramatically the inherent latency of vernier structure. The already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. The TDC has been simulated in 90nm CMOS technology. Operating from 50MHz reference frequency, it achieves a resolution better than 2ps assuming a signal bandwidth of 1.56MHz (OSR=16), for a minimum current consumption of 1.8mA from 1.2V.

Keywords

CMOS integrated circuits; VHF oscillators; delay lines; time-digital conversion; CMOS gated-ring-oscillator; CMOS technology; GRO; Vernier structure latency; bandwidth 1.56 MHz; delay lines; frequency 50 MHz; size 90 nm; small quantization noise; standard Vernier TDC; two-dimension Vernier time-to-digital converter; voltage 1.2 V; Delay; Delay lines; Flip-flops; Inverters; Phase frequency detector; Quantization; Radiation detectors;

fLanguage

English

Publisher

ieee

Conference_Titel

NORCHIP, 2012

Conference_Location

Cpenhagen

Print_ISBN

978-1-4673-2221-8

Electronic_ISBN

978-1-4673-2222-5

Type

conf

DOI

10.1109/NORCHP.2012.6403120

Filename

6403120