A genetic algorithm based optimization method for low vertical link density 3-dimensional Networks-on-Chip many core systems

The advantages of moving from 2-Dimensional Networks-on-Chip (NoCs) to 3-Dimensional NoCs for any application must be justified by the improvements in performance, power, latency and the overall system costs, especially the cost of Through-Silicon-Via (TSV). The trade-off between the number of TSVs and the 3D NoCs system performance becomes one of the most critical design issues. In this paper, we demonstrate a genetic algorithm (GA) based system optimization method, which can deliver the advanced system design setup through topology, routing algorithm, task mapping and tile placement. In comparison to the simulated annealing (SA) based design optimization method, our GA based method can achieve significant advantages. All the experiments have been done in GSNOC framework (written in SystemC-RTL), which can achieve the cycle accuracy and good flexibility.