Using SOI to achieve low-power consumption in digital

SOI offers an efficient static and dynamic power reduction through V_dd reduction without sacrificing speed performance. This V_dd reduction may be combined or not with other circuit techniques: MTCMOS where high-V_t transistors are connected in series between the core logic and ground/V_dd, gated clock cells where the clock is automatically diabled and not propagated. A low-power SOI circuit may be designed by gathering several blocks using different V_dd values depending on the speed requirement for each block. In such a case level-shifters are used to adapt the V_dd difference between the blocks (V_dd1 output to V_dd2 input and V_dd2 output to V_dd1 input). This requires the implementation of several power supply sources at system level. Implementing these techniques adds more design complexity and EDA tools must be able to support them. Making a comparison between bulk and SOI is not an easy task and it cannot be done only at transistor or cell level. The best way is to compare the results(speed, P_stat, P_dyn, area) obtained when a circuit is synthesized, placed and routed using bulk or SOI libraries, including the memories.