DocumentCode :
2839606
Title :
Edge-defined 90nm TFTs with adjustable VT in a 3-D compatible process
Author :
Nasrullah, Jawad ; Burr, James B. ; Tyler, G. Leonard ; Nishi, Yoshio
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., CA, USA
fYear :
2005
fDate :
3-6 Oct. 2005
Firstpage :
27
Lastpage :
29
Abstract :
This work focuses on the processing technology that achieves device VT adjustability in second and higher layers of short-channel stacked devices. The device mobility and adjusted subthreshold behavior reported here are, however, comparable to those in other TFT work.
Keywords :
carrier mobility; electron traps; nanotechnology; thin film transistors; 3D compatible process; 90 nm; device VT adjustability; device mobility; processing technology; short-channel stacked devices; thin film transistors; Electrodes; Lithography; Optical materials; Silicon; Thin film transistors; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOI Conference, 2005. Proceedings. 2005 IEEE International
ISSN :
1078-621X
Print_ISBN :
0-7803-9212-4
Type :
conf
DOI :
10.1109/SOI.2005.1563522
Filename :
1563522
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2839606
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