A 1V, Ka Band Prescaler with VTControl in 90nm CMOS SOI

Author

Ionita, Razvan ; Sanduleanu, Mihai A T ; Stikvoort, Eduard ; Vladimirescu, Andrei

Author_Institution

Inst. Superieur d´´Electronique de Paris

fYear

2005

fDate

6-6 Oct. 2005

Firstpage

41

Lastpage

43

Abstract

This paper presents a static frequency divider in a 90nm PD CMOS SOI process. The divider uses a novel D-latch topology and has an operation range of 8 to 28GHz with maximum sensitivity tuning of plusmn3GHz around 22GHz. The D-latches were implemented with NMOS transistors in R-NMOS logic. A new method is proposed for tuning the sensitivity curve of the prescaler by controlling the threshold voltage of the transistors. The V_T spread due to process variations is compensated too. The V_T control shows an improvement of the prescaler sensitivity with forward body-biasing voltages and an increase of the frequency range with reverse body-biasing voltages. At maximum operating frequency, the power consumption of the divider is 60mW (1V supply voltage) and the active area, including buffers, is 350 times 400mum²

Keywords

CMOS integrated circuits; MOSFET; frequency dividers; logic circuits; logic design; prescalers; silicon-on-insulator; voltage control; 1 V; 60 mW; 8 to 28 GHz; 90 nm; D-latch topology; Ka band prescaler; NMOS transistors; PD CMOS SOI process; R-NMOS logic; prescaler sensitivity; static frequency divider; voltage control; CMOS logic circuits; CMOS process; Circuit topology; Clocks; Coupling circuits; Frequency conversion; Inductors; Latches; Low voltage; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2005. Proceedings. 2005 IEEE International

Conference_Location

Honolulu, HI

ISSN

1078-621X

Print_ISBN

0-7803-9212-4

Type

conf

DOI

10.1109/SOI.2005.1563527

Filename

1563527