DocumentCode
2839980
Title
A back-to-face silicon layer stacking for three-dimensional integration
Author
Tan, C.S. ; Chen, K.N. ; Fan, A. ; Reif, R.
Author_Institution
Microsystems Technol. Labs., Massachusetts Inst. of Technol., Cambridge, MA, USA
fYear
2005
fDate
3-6 Oct. 2005
Firstpage
87
Lastpage
89
Abstract
We have successfully demonstrated a back-to-face ultra-thin silicon layer stacking based on low temperature wafer bonding and etch-back. This type of silicon layer stacking can be expanded to wafers with device and interconnect layers to fabricate three-dimensional integrated circuits (3D ICs). Electrical connection between layers can be achieved by interlayer vertical via formed by bonded Cu layers.
Keywords
copper; elemental semiconductors; integrated circuit interconnections; silicon; wafer bonding; 3D integrated circuits; 3D integration; Cu; Si; electrical connection; etch-back; interconnect layers; low temperature wafer bonding; ultra-thin silicon layer stacking; Chemicals; Dielectric substrates; Etching; Plasma temperature; Rough surfaces; Silicon devices; Stacking; Surface cleaning; Surface roughness; Wafer bonding;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 2005. Proceedings. 2005 IEEE International
ISSN
1078-621X
Print_ISBN
0-7803-9212-4
Type
conf
DOI
10.1109/SOI.2005.1563545
Filename
1563545
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