DocumentCode :
2840081
Title :
3D via etch development for 3D circuit integration in FDSOI
Author :
Knecht, J.M. ; Yost, D.R.W. ; Burns, J.A. ; Chen, C.K. ; Keast, C.L. ; Warner, K.
Author_Institution :
Lincoln Lab., Massachusetts Inst. of Technol., Lexington, MA, USA
fYear :
2005
fDate :
3-6 Oct. 2005
Firstpage :
104
Lastpage :
105
Abstract :
This paper describes the development of the 3D via etch process.The oxide via etch was developed in a Trikon Technologies low pressure, high density, helicon-based cluster tool. A response surface design-of-experiments (DOE) was performed varying etch pressure and wafer bias to examine their effect on etch profile and etch rates. An anisotropic etch is essential for high packing density. There was an excellent fit between the data and the model. Low pressure and high bias were required to give vertical profiles. Higher etch pressure caused excessive polymer deposition resulting in etch stop. Low wafer bias could not remove the deposited polymer fast enough, also resulting in etch stop.
Keywords :
design of experiments; etching; integrated circuit yield; silicon-on-insulator; 3D circuit integration; 3D via etch process; anisotropic etch; design-of-experiments; etch profile; etch rates; etch stop; fully-depleted silicon-on-insulator; helicon-based cluster tool; oxide via etch; polymer deposition; Contacts; Electric resistance; Etching; Laboratories; Polymers; Silicon; Testing; Three-dimensional integrated circuits; Tin; US Department of Energy;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOI Conference, 2005. Proceedings. 2005 IEEE International
ISSN :
1078-621X
Print_ISBN :
0-7803-9212-4
Type :
conf
DOI :
10.1109/SOI.2005.1563552
Filename :
1563552
Link To Document :
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