Effect of contact liner stress in high-performance FDSOI devices with ultra-thin silicon channels and 30 nm gate lengths

Author

Singh, D.V. ; Hergenrother, J.M. ; Sleight, J.W. ; Ren, Z. ; Nayfeh, H. ; Dokumaci, O. ; Black, L. ; Chidambarrao, D. ; Venigalla, R. ; Pan, J. ; Tessier, B.L. ; Nomura, A. ; Ott, J.A. ; Khare, M. ; Guarini, K.W. ; Ieong, M. ; Haensch, W.

Author_Institution

IBM Semicond. R&D Center, T. J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2005

fDate

3-6 Oct. 2005

Firstpage

178

Lastpage

179

Abstract

We have investigated for the first time the effect of stressed contact liners on the performance of fully depleted ultra-thin channel CMOS devices with a raised source/drain. Significant enhancement in mobility and drive current is observed in both nFETs and pFETs. The observed enhancement shows a strong dependence on the Si channel thickness and the height of the raised source/drain, consistent with stress simulations.

Keywords

MOSFET; carrier mobility; elemental semiconductors; silicon; silicon-on-insulator; stress effects; 30 nm; CMOS devices; FDSOI devices; Si; contact liner stress; drive current; nFET; pFET; silicon-on-insulator; ultra-thin silicon channels; CMOS technology; Compressive stress; Implants; MOS devices; Parasitic capacitance; Ring oscillators; Silicon; Stress measurement; Surfaces; Tensile stress;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 2005. Proceedings. 2005 IEEE International

ISSN

1078-621X

Print_ISBN

0-7803-9212-4

Type

conf

DOI

10.1109/SOI.2005.1563580

Filename

1563580