DocumentCode
2840563
Title
150nm SOI embedded SRAMs with very low SER
Author
Nelson, David K. ; Liu, Harry ; Golke, Keith ; Kohli, Anuj
Author_Institution
Honeywell DSES Plymouth, MN, USA
fYear
2005
fDate
3-6 Oct. 2005
Firstpage
188
Lastpage
190
Abstract
A split word line design technique that improves the soft error rate (SER) of high performance 150nm SOI embedded SRAMs is presented along with SER results.
Keywords
SRAM chips; embedded systems; silicon-on-insulator; 150 nm; embedded SRAM; silicon-on-insulator; soft error rate; split word line design; Charge carrier processes; Delay effects; Error analysis; Neutrons; Protection; Random access memory; Silicon; Single event upset; Testing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 2005. Proceedings. 2005 IEEE International
ISSN
1078-621X
Print_ISBN
0-7803-9212-4
Type
conf
DOI
10.1109/SOI.2005.1563583
Filename
1563583
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