Code restructuring for enhanced performance on a pipelined processor

The authors describe how code is restructured to enhance application performance on the Intergraph C400. The restructuring has several aims: to avoid or to reduce pipeline stalls, to enhance register and cache utilization, and to optimize control flow to reduce branch overhead and improve instruction scheduling scope. Avoiding pipeline stalls is a matter of locally and globally reordering computations so that the results are available before any attempt to use them. Improving register and cache utilization is done by restructuring algorithms to do as much as possible on data elements while they are held in registers or cache. In both these cases, the restructuring is controlled by dependence analysis similar to that found in vectorizing/parallelizing compilers. Branch overhead is reduced and instruction scheduling is improved by optimizing the block ordering of the program around the most frequently executed paths.<>