DocumentCode :
2840650
Title :
Ultra-low-voltage current-sense read circuits for CMOS SOI SRAMs
Author :
Thomas, Olivier ; Vladimirescu, Andrei ; Amara, Amara
Author_Institution :
Inst. Superieur d´´Electronique de Paris, France
fYear :
2005
fDate :
3-6 Oct. 2005
Firstpage :
205
Lastpage :
207
Abstract :
For SRAM circuits operated at 0.5V reliable readout of the stored information is challenging due to a voltage swing of tens of mV. Two readout topologies described in this paper for ultra-low-voltage (ULV) SOI-CMOS SRAMs exploit unique features of partially-depleted (PD)-SOI transistors to perform current rather than voltage sensing. The analysis presented leads to the dimensioning of the sense amplifier transistors for robust operation with a maximum number of cells per column of the SRAM. Simulations of the presented circuits demonstrate that the information stored in an SRAM with a four-transistor CMOS-SOI cell can be reliably accessed in 3ns with 180nW power consumption.
Keywords :
CMOS integrated circuits; SRAM chips; amplifiers; low-power electronics; silicon-on-insulator; 0.5 V; 180 nW; 3 ns; CMOS SOI SRAM; SRAM circuits; amplifier transistors; current-sense read circuits; partially-depleted-SOI transistors; power consumption; readout topologies; ultra-low-voltage read circuits; CMOS logic circuits; Circuit topology; Energy consumption; Feedback loop; Impedance; Operational amplifiers; Random access memory; Robustness; Transconductance; Voltage control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOI Conference, 2005. Proceedings. 2005 IEEE International
ISSN :
1078-621X
Print_ISBN :
0-7803-9212-4
Type :
conf
DOI :
10.1109/SOI.2005.1563589
Filename :
1563589
Link To Document :
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