An ECL RISC multiprocessor

Author

Foster, B. ; Alexander, C. ; Roberts, A. ; Roberts, D.

Author_Institution

Control Data Corp., Arden Hills, MN, USA

fYear

1991

fDate

Feb. 25 1991-March 1 1991

Firstpage

289

Lastpage

292

Abstract

The authors describe how an upgrade to the MIPS R6000 ECL chip set, the R6000A CPU and the R6020A SBC, implements a sophisticated coherent cache protocol to support multiple processor systems, and how software uses the system. Particular attention is given to the cache subsystem, the cache control attributes, the cache line states, and the software environment.<>

Keywords

buffer storage; multiprocessing systems; parallel architectures; reduced instruction set computing; ECL RISC multiprocessor; MIPS R6000 ECL chip set; R6000A CPU; R6020A SBC; cache control attributes; cache line states; coherent cache protocol; multiple processor systems; software environment; Application software; CMOS logic circuits; Central Processing Unit; Clocks; Control systems; Microprocessors; Protocols; Reduced instruction set computing; Software systems; System buses;

fLanguage

English

Publisher

ieee

Conference_Titel

Compcon Spring '91. Digest of Papers

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-8186-2134-6

Type

conf

DOI

10.1109/CMPCON.1991.128820

Filename

128820

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2840681