DocumentCode
2840709
Title
The NEC SX-3 supercomputer system
Author
Watanabe, T.
Author_Institution
NEC Corp., Tokyo, Japan
fYear
1991
fDate
Feb. 25 1991-March 1 1991
Firstpage
303
Lastpage
308
Abstract
The architecture of the NEC SX-3 supercomputer system is introduced. The system configuration, featuring a multiprocessor, is described, and the instruction functions and internal hardware structure, including multiple vector pipelines and a scalar unit with cache, are introduced. Performance results are shown.<>
Keywords
NEC computers; computer evaluation; multiprocessing systems; parallel architectures; performance evaluation; pipeline processing; NEC SX-3 supercomputer system; cache; hardware structure; instruction functions; multiple vector pipelines; multiprocessor; performance results; scalar unit; system configuration; Arithmetic; Computer architecture; Concurrent computing; Hardware; Large-scale systems; National electric code; Pipelines; Process control; Registers; Supercomputers;
fLanguage
English
Publisher
ieee
Conference_Titel
Compcon Spring '91. Digest of Papers
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-8186-2134-6
Type
conf
DOI
10.1109/CMPCON.1991.128822
Filename
128822
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